AN3316 datasheet(6/42 Pages) STMICROELECTRONICS

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Power consumption factors

AN3316

6/42

Doc ID 18232 Rev 2

Figure 2.

Global clock tree architecture

It is possible to decrease power consumption through following features:

●

Reduced number of directly clocked lines (see red circle on Figure 2)

●

Reduced local clock rates through peripheral bus division (see blue circle on Figure 2)

ModeEntry Module is also structured to help reduce dynamic power consumption as:

●

Allows to clock-gate each peripheral independently. So, power saving can be achieved

by clock-gating peripherals not used in the application.

●

Allows to switch-off the CPU which is the most power-hungry part in the device. For

example, while waiting for an ADC conversion to complete.

CMU

OSC

16MHz

IRC

16MHz

OSC

32KHz

IRC

128KHz

FMPLL

RESET

SAFE

INT

system_clk

div 1 to 32

CLKOUT

Selector

div 1/2/4/8

CLOCK OUT

SWT

(Watchdog)

API / RTC

Peripheral Set 1

Peripheral Set 2

Peripheral Set 3

System

Clock

Selector

(ME)

div 1 to 15

Core

Platform

osca_clk_div

irc_fast_div

osca_clk

osca_fast

fmplla_clk

div 1 to 32

oscb_clk_div

irc_fast_div

irc_slow_div

irc_fast

osca_clk

oscb_clk

irc_slow

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