AN4173

ADC 10-bit timing configuration parameters

Doc ID 023727 Rev 3

9/22

The total evaluation phase duration is given by:

Equation 6

where INPCMP

The total conversion duration of ADC is given by:

Equation 7

where TCK depends on the peripheral set 3 clock divider.

ADC Clock Frequency:

In SPC560Cxx, SPC560Dxx and SPC560Bxx devices (256 KB, 512 KB and 1.5 MB) there

is a bit in the ADC MCR register that allows to select if the ADC clock frequency is half or

equal to the Peripheral Set Clock frequency. The bitfield is the ADCLKSEL.

In SPC564Bxx e SPC56ECxx devices the ADC clock frequency is always set as half of the

Peripheral Set Clock.

2.2

SPC56xBxx and SPC56xCxx family ADC 10-bit timing

properties

The integration of the ADC 10-bit module in the SPC56xBxx and SPC56xCxx products

leads to some further constraints to guarantee the performance indicated in the

datasheet/electrical characteristics. In particular sampling time and conversion times must

respect minimum values, which are:

●

sampling time must be equal or greater than 500 ns.

●

the ADC clock range is between 6 MHz to 32 MHz.

●

evaluation time must be equal or greater than 500 ns.

●

the minimum conversion time reachable is 1.05 us.

Table 1 gives the ADC sampling and conversion timing, at 5V / 3.3 V, for the ADC, using the

suggested parameters:

T

eval

10

T

biteval

×

10

INPCMP

T

CK

×

()

×

==

T

conv

T

sample

T

eval

ndelay

T

CK

×

()

++

()

=

Table 1.

ADC sampling and conversion timing

Clock

(MHz)

TCK

(µs)

INPSAMP

IMPCMP

INPLATCH

ndelay

(µs)

(µs)

(µs)

TCK

TCK

6

0.167

4

1

0

0.5

0.583

1.667

2.333

14

3.500

7

0.143

4

1

0

0.5

0.500

1.429

2.000

14

3.500

8

0.125

5

1

0

0.5

0.563

1.250

1.875

15

4.500