Product description

AN2348

2/17

Doc ID 12282 Rev 5

1

Product description

Flip Chips are manufactured with a wafer level process that STMicroelectronics has

developed by attaching solder bumps on I/O pads of the active wafer side, thus allowing

bumped dice to be produced. The I/O contact layout can be either matrix shape or set in

periphery. No redistribution layer is used. This allows parasitic inductances coming from the

redistribution metal tracks to be minimized.

Lead-free bump composition is 98.25% Sn, 1.2% Ag, 0.5% Cu, 0.05% Ni. This is fully

compatible with standard lead-free reflow processes. The bump dimension (255 µm bump

diameter) allows the pick and place process to be compatible with existing equipment (in

particular with equipment used for Ball Grid Array - BGA packages) and makes it also

compatible with the PCB design rules used for standard ICs.

Optional coating on the flat side of the package is available.

These components are delivered in tape and reel packing with the bumps turned down

(placed on the bottom of the carrier tape cavity). The other face of the component is flat and

allows picking as in the standard SMD packages.

Devices are 100% electrically tested before packing. The product references are marked

on the flat side of the device.

2

Mechanical description

Mechanical dimensions of Flip Chips are provided through a product example in Figure 2.

Bumps are lead-free. Bump composition is 98.25% Sn, 1.2% Ag, 0.5% Cu, 0.05% Ni alloy

with a near eutectic melting point of 218 to 227 °C. Die size and bump count are adapted to

the connection requirements.

Figure 2.

Mechanical dimensions of a 5 x 5 bump matrix array (sample).

Note:

The package height of 0.605 mm (0.650 mm for optionally coated packages) is valid for a

die thickness of 0.40 mm.

1.97 mm ± 30 µm

255 µm ± 40

200 µm ± 20

200 µm ± 20

400 µm ± 40

605 µm ± 55

650 µm ± 60

Optional

coating