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AN1518 Datasheet(PDF) 7 Page - STMicroelectronics |
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AN1518 Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 30 page ![]() AN1518 Functional description 7/30 3.3 Oscillator & synchronizer Figure 6 shows the block diagram of the oscillator circuit. The Clock Generator provides the switching frequency of the device, which is internally fixed at 250 kHz. The Frequency Shifter block acts to reduce the switching frequency in case of strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is the input of the Ramp Generator and Synchronizer blocks. The Ramp Generator circuit provides the sawtooth signal, used for PWM control and internal voltage feed-forward, while the synchronizer circuit generates the synchronization signal. The device also has a synchronization pin which can work both as Master and Slave. As Master, it serves to synchronize external devices to the internal switching frequency, and as Slave to synchronize itself using an external signal up to 500 kHz. In particular, when connecting together two devices the one with the lower switching frequency works as a Slave and the other as Master. To synchronize the device, the SYNC pin must pass from a low level to a level higher than the synchronization threshold with a duty cycle that can vary from approximately 10% to 90%, depending also on the signal frequency and amplitude. The frequency of the synchronization signal must be, at a minimum, higher than the internal switching frequency of the device (250 kHz). Figure 6. Oscillator circuit block diagram 3.4 Current protection The L5973D features two types of current limit protection: pulse-by-pulse and frequency foldback. The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in Figure 7. The output power PDMOS transistor is split into two parallel PDMOS transistors. The smallest one includes a resistor in series, RSENSE. The current is sensed through RSENSE and if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. Since the minimum switch ON time (necessary to avoid false a overcurrent signal) is too short to obtain a sufficiently low duty cycle at 250 kHz, the output current, in strong overcurrent or short circuit conditions, could increase |
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