AN2381 datasheet(9/47 Pages) STMICROELECTRONICS

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AN2381

Electrical connection and board layout hints

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Electrical connection and board layout hints

2.1

Electrical connection

The typical electrical connection of the LIS3LV02DL is shown in Figure 2

Figure 2.

LIS3LV02DL electrical connection

The device core is supplied through Vdd line (Vdd typ=2.5V) while the I/O pads are supplied

through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10

µF Al) should

be placed as near as possible to the pin 13 of the device.

Both the voltage supplies must be present at the same time to have proper behavior of the

IC. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication

bus.

The central die pad and pin #1 indicator are physically connected to GND.

The functionality of the device and the measured acceleration data are

selectable/accessible through the I2C/SPI interface.

When using the I2C, CS must be tied high while SDO must be left floating.

2.2

Power supply and board layout hints

The LIS3LV02DL is designed for a voltage supply spanning from 2.16V up to 3.6V.

The typical current consumption in normal mode at 2.5V is 600

µA.

Adequate power supply decoupling is required to ensure IC performances. The optimum

decoupling is achieved by using two capacitors of different types that target different kinds of

noise on the power supply leads. To attenuate high frequency transients, spikes, or digital

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

Vdd_IO

10uF

Vdd

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

100nF

GND

LIS3LV02DL

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