AN2381 datasheet(23/47 Pages) STMICROELECTRONICS

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AN2381

Registers Description

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IEN bit is used to switch the value present on data-ready pad between Data-ready signal

and Interrupt signal. At power up the Data-ready signal is chosen. It is however necessary to

modify DRDY bit to enable Data-ready signal generation.

DRDY bit is used to enable DataReady pad activation. If DRDY bit is ‘0’ (default value) on

DataReady pad a ‘0’ value is present. If a DataReady signal is desired it is necessary to set

to ‘1’ DRDY bit. DataReady signal goes to ‘1’ whenever a new data is available for all the

enabled axes. For example if Z-axis is disabled, DataReady signal goes to ‘1’ when new

values are available for both X and Y axes. DataReady signal comes back to ‘0’ when all the

registers containing values of the enabled axes are read. To be sure not to loose any data

coming from the accelerometer data registers must be read before a new DataReady rising

edge is generated. In this case DataReady signal will have the same frequency of the data

rate chosen.

SIM bit selects the SPI Serial Interface Mode. When SIM is ‘0’ (default value) the 4-wire

interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire

interface mode output data are sent to SDA_SDI pad.

DAS bit selects between 12 bit right justified and 16 bit left justified data representation. The

first case is the default case and the most significant bits are replaced by the bit

representing the sign.

5.2.3

CTRL_REG3 (22h)

Control register #3

ECK bit selects whether the clock used in the core comes from internal oscillator or from

external pad OSC_IN. In the latter case internal oscillator is switched off and the pin Pull-

Down is disabled thus reducing power consumption. External clock must be in the range of

1.045 MHz +/- 10% and must have a duty cycle of 50%.

HPDD bit permits to select either filtered or not filtered data to feed the Signal Processing

(Direction Detection) block as described in Figure 11. When HPDD is set to ‘0’ (default

ECK

HPDD

HPFF

FDS

res

CFS1

CFS0

ECK

External Clock. Default value: 0

(0: clock from internal oscillator; 1: clock from external pad)

HPDD

High Pass filter enabled for Direction Detection. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPFF

High Pass filter enabled for Free-Fall. Default value: 0

(0: filter bypassed; 1: filter enabled)

FDS

Filtered Data Selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter)

CFS1, CFS0

High-pass filter Cut-off Frequency coefficient Selection

(00: HPc = 512

01: HPc = 1024

10: HPc = 2048

11: HPc = 4096)

res

Reserved. These bit are reserved for future enhancements.

Best to be left to their default value (10 binary)

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