Layout guidelines

AN3971

20/28

Doc ID 022119 Rev 2

7

Layout guidelines

PCB layout is very important, especially for the SPV1020, in order to minimize noise, high

frequency resonance problems, and electromagnetic interference.

Paths between each inductor and the relative pin must be designed with the same

resistance. Different resistance between the four branches can be the root cause of

unbalanced currents flowing between the four branches. Unbalanced currents can imply

damage and a bad tracking of the MPPT.

It is essential to keep the paths as small as possible where the high switching current

circulates, to reduce peak voltages, radiation and resonance problems.

Large traces for high current paths and an extended ground plane under the metal slug of

the package help reduce noise and heat dissipation, and furthermore, increase the

efficiency. Depending on the maximum power of the application, two or more ground plane

layers may be required, and in this case thermal vias must connect the ground plane layers.

The number of layers, their thickness and number of thermal vias, affect the thermal

application it is suggested to refer to the TN0054 technical note.

The boost capacitors, output and input capacitors, must be placed as close as possible to

the pins of the IC. Output capacitance must be shared in at least four capacitors, each one

avoid pick-up noise.

Figure 15.

STEVAL-ISV005V2 (top view)

AM10267V1