AN4191

14/20

Doc ID 023815 Rev 1

3.2

Synchronous buck converter for motherboard: LS false turn-

on risk enhancement

In Figure 16, the schematic of a single-phase synchronous buck converter is shown

while Q1-3 is the low-side FET.

Figure 16.

Schematic of a single-phase synchronous buck converter

The LS device can be affected by the so-called “LS false turn-on,” which can be potentially

dangerous for the MOSFET itself and the reliability of the entire converter. When the high-

side turns on, a high dV/dt appears across the low-side device (Figure 17). Through the

If the total resistance formed by the intrinsic, external, and driver resistances is much lower

than the equivalent MOSFET impedance between gate and source, this current flows

through the above mentioned resistive path. This causes a spurious bouncing across gate

and source MOSFET pins; if this induced voltage is higher than minimum threshold voltage,

the LS can be partially turned on, creating a low-resistance path between supply voltage

and GND. In other words, undesired power dissipation is present in each switching cycle,

worsening the converter efficiency, thermal management, and reliability.

Figure 17.

Cdv/dt false turn-on event

AM16423V1

AM16424V1