AN4213 datasheet(14/42 Pages) STMICROELECTRONICS

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Designing a TM PFC

AN4213

14/42

DocID023984 Rev 2

where, as given in

Equation 8:

The switching losses in the Power MOSFET occur only at turn-off because of TM operation

and can be expressed by:

Equation 22

This equation represents the crossing between the Power MOSFET current that decreases

linearly during the fall time and the voltage on the Power MOSFET drain that increases. In

fact during the fall time the current of the boost inductor flows into the parasitic capacitance

of the Power MOSFET, charging it. For this reason switching losses depend on the total

drain capacitance.

At turn-on the losses are due to the discharge of the total drain capacitance inside the

Power MOSFET itself.

The capacitive losses are given by:

Equation 23

Where C

is the total drain capacitance and V

MOS

is the drain voltage at Power MOSFET

turn-on.

Based on the above considerations, the Power MOSFET device selected is the

STL13N60M2. This device is an N-channel Power MOSFET developed using a new

generation of MDmesh II Plus

low Q

. This revolutionary Power MOSFET associates a

vertical structure to the company's strip layout to yield one of the world's lowest on-

resistance and gate charge. This choice is confirmed by the good electrical performance

and thermal behavior.

3.3.6

Boost diode selection

A fast-recovery boost diode is used. The value of its DC and RMS current (see

Equation 9),

useful for the calculation of the losses, are both:

Equation 24

The conduction losses can be estimated as follows:

Equation 25

Where, V

(threshold voltage) and R

(differential resistance) are parameters of the diode.

OUT

Lpk

SWrms

min

−

()

Lrms

OUT

switch

()

MOS

CAP

OUT

DRMS

DON

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