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AN1775 Datasheet(PDF) 4 Page - STMicroelectronics |
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AN1775 Datasheet(HTML) 4 Page - STMicroelectronics |
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4 / 27 page ![]() 1 Power management AN1775 4/27 1 Power management 1.1 Overview The chip is powered by an external 3V3 supply(V33: 2.7 to 3.6 V, AVDD: 3.0 to 3.6 V). All I/Os are 3V3-capable. An internal Voltage Regulator generates the supply voltage for core logic (~=1.8V). The two V18 pins must be connected to external stabilization capacitors. The following figure indicates the recommended configuration for the power supply pins: Figure 1. STR71x power supply pins 1.2 Power management block The following figure describes the power management block implemented on the STR71x devices. Figure 2. Power Management Block The STR71x power management block has two regulators: ● The Main Voltage Regulator MVR. ● The Low Power Voltage Regulator LPVR. Note the following remarks about the two regulators: ● Both regulators can be switched-off by software STR71x V33 V18 V18BKP VSS VSSBKP GND 10µF 33nF GND 1µF GND V33IO-PLL VSSIO-PLL 3V3 I/O circuitry 3.3 V CORE Main Voltage Backup block Low Power Voltage 1.8 V switch Regulator (LPVR) Regulator (MVR) see note 1 GND 10µF 33nF V18 GND 1µF V18BKP 3V3 V33 |
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