UPD6461GS datasheet(21/60 Pages) NEC

21 / 60 page

µPD6461, 6462

2.3 POWER-ON CLEAR FUNCTION

The internal state of the IC is unstable immediately after the power is turned on. It is therefore necessary to keep the

PCL pin low for the time shown below to allow the system to initialize. This power-on clear places the system in the following

state:

•

Test mode is not specified.

•

All character data in video RAM (12 rows

× 24 columns) is cleared (to display-off data (FEH:

µPD6461/7EH: µPD6462)) and

blinking is turned off.

•

The video RAM write address is (row 0, column 0).

•

The character size is single (minimum) for all rows.

•

The output distribution format is set to the default (the VC1 and VC2 bits are set to 0).

•

Display is turned off and LC oscillation is turned on.

The time required for power-on clear is calculated as follows. No commands must be input during this time.

Time required for power-on clear = tPCLLNote + {Time required for clearing video RAM}

= 10(

µs) + {10(µs) + 12/fOSC(MHz) × 288}

fOSC(MHz) : LC oscillation frequency or external clock frequency

Note Refer to POWER-ON CLEAR SPECIFICATIONS in 6. ELECTRICAL CHARACTERISTICS.

A dot clock input (to the OSCIN pin) is necessary to clear video RAM. Input a dot clock when an external clock input is

selected.

UPD6461GS Datasheet(PDF) 21 Page - NEC