AN2797

DDR memory interface

Doc ID 14841 Rev 1

7/23

Figure 1.

An example of an effective low-inductance decoupling capacitor location

and mounting layout.

2.2

Data signal routing

Signal trace geometries:

Width: 4 mil to 5mil, 0.1 mm to 0.13 mm

Minimum space: 4 mil to 5 mil, 0.1 mm to 0.13 mm

Trace to trace spacing should be increased where routing density allows to reduce crosstalk.

A minimum separation of 10 mils is recommended, except for BGA escape areas.

All signals should be routed referenced to a ground plane, not a power plane.

Do not route any DDR2 signals on top of split planes or voids of copper.

Do not route any other signals inside or on top of the area reserved for DDR.

Maintain adequate separation between DDR signals and any other signals.

Traces routed near the edge of a reference plane should maintain at least 30 mil gap to the

edge of the reference plane.

To minimize the reflection all the traces should have an impedance of 55 Ohm ± 10%.