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AN2797 Datasheet(PDF) 9 Page - STMicroelectronics

Part # AN2797
Description  PCB layout guidelines for SPEAr600
PDF  23 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2797 Datasheet(HTML) 9 Page - STMicroelectronics

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AN2797
DDR memory interface
Doc ID 14841 Rev 1
9/23
other trace lengths must be adjusted to meet within Ltol. The worksheet computes
Lmax for you.
4.
With the longest total trace known (Lmax), the shortest total trace length permitted
(Lmin) can be calculated by Lmin = Lmax-Ltol. Record the value of Lmin.
Note:
Lmin is the total of PCB + substrate trace lengths. The worksheet computes Lmin for you.
5.
Identify all signals within each data lane whose total length is less than Lmin. Tabulate
this difference. The worksheet does this for you.
6.
Add the length computed in step 5 to the traces. The worksheet does this for you.
Table 1.
Package substrate trace length
Signal name
Ball
Package substrate trace length
(mm)
(mils)
DDR_ADD_0
AB3
9.0
354
DDR_ADD_1
AB4
8.2
323
DDR_ADD_2
AA4
7.5
295
DDR_ADD_3
Y4
7.3
287
DDR_ADD_4
W4
5.7
224
DDR_ADD_5
W5
5.7
224
DDR_ADD_6
Y5
6.4
252
DDR_ADD_7
AA5
5.9
232
DDR_ADD_8
AB5
7.6
299
DDR_ADD_9
AB6
8.3
327
DDR_ADD_10
AA6
5.6
220
DDR_ADD_11
Y6
5.9
232
DDR_ADD_12
W6
5.4
213
DDR_ADD_13
W7
4.6
181
DDR_ADD_14
Y7
5.4
213
DDR_BA_0
Y9
3.9
154
DDR_BA_1
W9
4.4
173
DDR_BA_2
W10
6.6
260
DDR_RAS
AB7
7.0
276
DDR_CAS
AA7
6.6
260
DDR_WE
AA8
5.7
224
DDR_CLKEN
AB8
7.0
276
DDR_CLK_P
AA9
5.4
213
DDR_CLK_N
AB9
5.8
228
DDR_CS_0
Y8
5.3
209
DDR_CS_1
W8
4.8
189



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