SPEAr interrupt logic

AN3129

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Doc ID 16927 Rev 1

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SPEAr interrupt logic

SPEAr is a family of embedded MPUs based on the ARM core. The embedded MPU uses

the PL190 vectored interrupt controller (VIC) IP. Together they provide facilities to use fast

interrupts as highest priority interrupts. Fast interrupt features are supported by both the

ARM core and the VIC. This VIC IP can be configured to select any hardware source to

interrupt ARM core as either IRQ or FIQ.

Figure 1.

SPEAr platform interrupt logic

The order of priority for hardware interrupts (from higher to lower) is as follows:

1.

Fast interrupt request (FIQ) interrupts

2.

Vectored IRQ interrupts

3.

Non-vectored IRQ interrupts.

FIQs are intended for fast, low-latency interrupt handling. In FIQ mode, the ARM core uses

seven 32-bit banked registers, which enable the VIC to process interrupts as quickly as

possible.

Multiple interrupts can be handled as FIQs, but in this case the IRQ vector needs to be

loaded in the program counter (PC). In order to reduce interrupt latency, it is advised to use

a single FIQ source, because the ISR can be directly executed without determining the

source of the interrupt.

As the Linux kernel never disables FIQs they have ultimate priority over anything else in the

system. When using an FIQ, the FIQ latency will be the time it takes the CPU to enter your

FIQ function. Moreover an FIQ can preempt Linux kernel code and IRQ handlers and it can

also be used for faster response to interrupts.

Note:

The use of an FIQ in place of an IRQ does not require any hardware (wiring) modifications

on the SPEAr board. The VIC has a 32-bit register (VICINTSELECT) which can toggle an

IRQ source to raise an FIQ instead of the default mechanism of IRQ.

Interrupt logic

Interrupt sources

Vectored

interrupt

controller

ARM

FIQ

IRQ