AN3132

DDR overview

Doc ID 16955 Rev 1

9/24

For example, the situation for the cut 128 Mb x 8 in eight and four bank mode is shown

below:

●

128 Mb x 8 (eight bank mode, all 3 bank address bits are used)

–

User_address [0] = datapath;

–

User_address [10:1] = column address;

–

User_address [13:11] = bank address;

–

User_address [27:12] = row address;

–

User_address [28] = chip select;

●

128 Mb x 8 (four bank mode, only 2 bits are used for the bank address)

–

User_address [0] = datapath;

–

User_address [10:1] = column address;

–

User_address [12:11] = bank address;

–

User_address [26:13] = row address;

–

User_address [27] = chip select;

SPEAr600 supports DDR1 and DDR2 devices. The memory controller needs to be

configured once at system startup depending on the memory type, size, and vendor and on

the frequency you want to work with.