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AN3137

Methods for precision improvement

Doc ID 16983 Rev 3

29/42

Figure 16.

Effect of sampling time extension

If the maximum register value of the sampling time setting is reached and the problem is still

present, you need a more complex solution which is applicable also for measurements of

source with extra high internal impedance (see the section Workaround for extra high

impedance sources below).

Note that for this application you must take into account not only the internal sampling

capacitance, but also any external parasitic capacitance (in parallel to Cext), such as: pin

capacitance, PCB path capacitance, etc.

Do not add any external capacitor (Cext) to the input pin when applying this workaround. Its

capacity will increase the timing constant (Rin * Csh || Cext) and the problem will remain.

Workaround for extra high impedance sources

This workaround consists of 2 parts: a hardware change and a software change.

Hardware change:

The hardware change consists of adding a large external capacitor (Cext) to the input pin.

The capacity size connected to the input pin must reach the value that causes the

discharging of the internal sampling capacity Csh to the external capacitor Cext without

increasing the voltage on Cext to more than 0.5 lsb. For example:

If the internal capacitor (Csh = 16 pF) is charged to full scale (Umax, which corresponds to

4096 lsb), then the external capacitor Cext must be charged at maximum 0.5 lsb voltage

level (Ulsb) after discharging Csh to it. The capacity of Cext will then be:

The closest larger standard value chosen here is: Cext = 150 nF.

ext

max

lsb

--------------

⋅

≥

16pF

4096

0.5

-------------

131nF

≈

⋅

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