AN3171

Hardware considerations

Doc ID 17229 Rev 1

5/14

1

Hardware considerations

1.1

Pinout comparison

Figure 1 and Figure 2 show the logic diagrams and the pinouts of the M24LR64-R and

M24C64 devices, respectively.

Figure 1.

M24LR64-R and M24C64 logic diagrams

M24LR64-R AC0/AC1 pins: due to its RF capability, the M24LR64-R dual interface

EEPROM features two inputs (AC0 and AC1) to connect the RF antenna.

Consequently, two inputs present in the M24C64 are not offered in the M24LR64-R: these

are E2 and Write Control (WC).

Practically, this means that you will be able to use up to four M24LR64-R devices (defined by

E0, E1) on the same I²C bus, compared to eight devices (defined by E0, E1, E2) for the

M24C64.

The Write Control input (WC) is used to write-protect the M24C64. The M24LR64-R can

also be protected but in a different way, using the I2C_Write_Lock bits.

Figure 2.

M24LR64-R and M24C64 pinouts

positioned likewise in the two devices.

AC0 and AC1 are connected to pin 2 and pin 3, respectively. They have to be next to each

other for RF capability requirements. As a result, E1 was moved to pin 7 in the M24LR64-R,

whereas it is connected to pin 2 in the M24C64.