AN3250

Designing an M24LR64-R multi-bank application

Doc ID 17761 Rev 1

3/16

2

Designing an M24LR64-R multi-bank application

2.1

M24LR64-R datasheet for more details.

Each device is accessed according to its value defined by the Device Select code.

The M24LR64-R offers two Chip Enable pins, E0 and E1. These signals are used to set the

values that are to be looked for on bits b2 and b1 of the 7-bit Device Select code.

Figure 4.

Logic diagram

Table 1.

Device Select code description

1.

The most significant bit (b7) is sent first.

2.

E0 and E1 are compared against the respective external pins on the memory device.

RW

b7

b6

b5

b4

b3

b2

b1

b0

Device Select code

1010

3.

E2 is not connected to any external pin. It is however used to address the M24LR64-R system area as

described in the datasheet.

E1

E0

RW

Table 2.

Signal descriptions

Signal name

Function

Direction

E0, E1

Chip Enable

Input

SDA

Serial Data

I/O

SCL

Serial Clock

Input

AC0, AC1

Antenna coils

I/O

AI15106b

2

E0-E1

SDA

VCC

M24LR64-R

SCL

VSS

AC0

AC1