AN3320 datasheet(9/29 Pages) STMICROELECTRONICS

9 / 29 page

AN3320

Power supplies

Doc ID 18267 Rev 2

9/29

Figure 2.

Power supply scheme

Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and

1 µF) must be connected.

VREF+ is either connected to VREF or to VDDA.

N is the number of VDD and VSS inputs.

Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet to connect REGOFF and IRROFF

pins.

1.3

Reset & power supply supervisor

1.3.1

Power on reset (POR) / power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from

1.8 V.

The device remains in the Reset mode as long as VDD is below a specified threshold,

VPOR/PDR, without the need for an external reset circuit. For more details concerning the

power on/power down reset threshold, refer to the electrical characteristics in

STM32F20xxx/21xxx datasheets.

On WLCSP66 package if IRROFF pin is set to VDD (in that case REGOFF pin must not be

activated, refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details ),

the PDR is not functional. Then the VDD can lower below 1.8 V, but the external circuitry

must ensure that reset pin is activated when VDD/VDDA becomes below 1.65 V.

AN3320 Datasheet(PDF) 9 Page - STMicroelectronics