RM0312 datasheet(100/275 Pages) STMICROELECTRONICS

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Independent watchdog (IWDG)

RM0312

100/275

DocID022352 Rev 3

15.3

IWDG registers

15.3.1

Key register (IWDG_KR)

Address offset: 0x00

Reset value: 0xXX

15.3.2

Prescaler register (IWDG_PR)

Address offset: 0x01

Reset value: 0x00

654

3210

KEY[7:0]

Bits 7:0 KEY[7:0]: Key value

The KEY_REFRESH value must be written by software at regular intervals, otherwise the watchdog

generates an MCU reset when the counter reaches 0.

If the IWDG is not enabled by option byte (see datasheet for option byte description), the

KEY_ENABLE value is the first value to be written in this register.

KEY_ENABLE value = 0xCC

Writing the KEY_ENABLE value starts the IWDG.

KEY_REFRESH value = 0xAA

Writing the KEY_REFRESH value refreshes the IWDG.

KEY_ACCESS value = 0x55

Writing the KEY_ACCESS value enables the access to the protected IWDG_PR and IWDG_RLR

registers (see Section 15.2).

654

3210

Reserved

PR[2:0]

Bits 7:3 Reserved

Bits 2:0 PR[2:0]: Prescaler divider

These bits are write access protected (see Section 15.2). They can be written by software to select the

prescaler divider feeding the counter clock.

000: divider /4

001: divider /8

010: divider /16

011: divider /32

100: divider /64

101: divider /128

110: divider /256

111: Reserved

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