RM0319 datasheet(93/368 Pages) STMICROELECTRONICS

93 / 368 page

RM0319

Serial NOR Flash controller (SMI)

Doc ID 022640 Rev 3

93/368

Serial NOR Flash controller (SMI)

This chapter focuses on SMI functionality and operation.

For technical details about the programmable registers related to the SMI, refer to the SMI

registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

7.1

Overview

SPEAr320S provides a serial memory interface (SMI), acting as an AHB slave interface

(32-, 16- or 8-bit) to SPI-compatible off-chip memories. SMI allows the CPU to use these

serial memories for both data storage and code execution.

7.2

Main features

●

Supports a group of SPI-compatible Flash and EEPROM devices:

–

Micron M25Pxxx, M45Pxxx

–

STMicroelectronics M95xxx, except M95040, M95020 and M95010

–ATMEL AT25Fxx

–YMC Y25Fxx

–

SST SST25LFxx

●

Acts always as a SPI master and up to 2 SPI slave memory devices are supported

(through as many chip select signals), with up to 16 MB address space each.

●

The SMI clock signal (SMI CLK) is generated by SMI and inputs to all slaves. It can be

up to 50 MHz in fast read mode (or 20 MHz in normal mode), and it can be controlled

by a programmable 7-bit prescaler allowing 127 different clock frequencies.

RM0319 Datasheet(PDF) 93 Page - STMicroelectronics