RM0319 datasheet(100/368 Pages) STMICROELECTRONICS

100 / 368 page

Serial NOR Flash controller (SMI)

RM0319

100/368

Doc ID 022640 Rev 3

taking into account up to 9 clock periods in addition to 64 clock periods required to both

send command to serial Flash memory (1-byte opcode + 3-bytes address) and receive back

32 bits.

●

Besides, under the same assumption, the nominal latency for a 32 bit single write to a

non-incrementing serial Flash address is:

●

5 tAHB maximum, if PRESC = 1 (that is, tAHB = tSMI_CLK).

●

(2 tSMI_CLK + 3 tAHB) maximum, if PRESC > 1 (that is, tAHB ≠ tSMI_CLK, and specifically

tSMI_CLK > tAHB).

In case of AHB read burst transfers, the maximum latency for all transfers after the first is the

same as data size, that is (32 tSMI_CLK) for a word transfer, (16 tSMI_CLK) for a half-word and

(8 tSMI_CLK) for a byte, because of no mandatory extra commands (instruction opcode and

address).

Moreover, for AHB write burst transfers, the maximum latency for the 2nd transfer is (data

size + opcode + address bytes) whereas it is the same as data size for following transfers.

However, nominal latency can be increased by:

●

Ongoing SMI transfer (read, write, read status register command or write enable

command)

●

Deselect time programming (field TCS in SMI_CR1 register), which adds (TCS + 1) ·

SMI_CLK periods

●

Busy / Idle transfer on AHB bus

●

Fast read which adds 1 dummy byte

●

Hold programming (field HOLD in SMI_CR1 register)

●

Boot delay time (Section 7.5.1)

●

Frequency change

●

Programming on-going

7.5

Programming examples

7.5.1

Booting from external memory

The device allows an external boot from a serial Flash only located at Bank0 (which is

enabled after power-on reset). During the boot phase, the following instructions sequence is

automatically sent to bank0:

●

Release from deep power-down (opcode 8’hAB, Table 34), in order to be able to boot

on this bank even if it was in deep power-down mode.

●

29 µs delay to ensure Bank0 is successfully released.

●

Read status register (opcode 8’h05), in order to check that bank0 is neither in write nor

in erase cycle.

●

Read data bytes (opcode 8’h03) at memory start location (that is, 32’h0) with a 19 MHz

clock frequency.

Note:

All memory banks other than Bank0 are disabled at reset and they must be enabled by

setting dedicated BE bits in SMI_CR1 register before they can be accessed.

If an AHB request occurs while either the WEN bit or the RSR bit (both in SMI_CR2 register,

is set, the on-going command is first finished before the request from AHB is sent to the

memory.

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