RM0319 datasheet(225/368 Pages) STMICROELECTRONICS

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RM0319

I2C bus ports (I2C)

Doc ID 022640 Rev 3

225/368

I2C bus ports (I2C)

This chapter focuses on I2C functionality and operation.

For technical details about the programmable registers related to the I2C, refer to the I2C

registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

17.1

Overview

The I2C controller provides an APB interface to the processor to access the two-wire serial

I2C bus. It can be used to connect any device which conforms to the I2C-Bus Specification

from Philips.

17.2

Main features

●

Compliance to the I2C-bus specification from Phillips

●

Operates in three different modes:

–

Standard-speed mode (data rates up to 100 Kb/s)

–

Fast-speed mode (data rates up to 400 Kb/s)

–

High-speed mode (data rates up to 3.4 Mb/s)

●

Provides clock synchronization.

●

Supports either master (only in a single master environment) or slave I2C operation

mode.

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Supports only slave operation in multimaster environment;

●

Provides 7-bit or 10-bit addressing both in master and slave mode;

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Supports 7-bit or 10-bit combined format transfers.

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Provides slave bulk transfer mode.

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Ignores CBUS addresses (an older ancestor of I2C that used to share the I2C bus).

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Transmits and receives buffers.

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Provides interrupt or polled-mode operation.

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Handles bit and byte waiting at all bus speeds.

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Provides digital filter for the received SDA and SCL lines.

●

Provides a DMA handshaking interface compatible with SPEArTM Basic DMA controller

handshaking interface.

●

Provides 8-bit or 16-bit wide transaction on the APB bus.

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