RM0319 datasheet(268/368 Pages) STMICROELECTRONICS

268 / 368 page

LCD display controller (CLCD)

RM0319

268/368

Doc ID 022640 Rev 3

LCD display controller (CLCD)

This chapter focuses on CLCD functionality and operation.

For technical details about the programmable registers related to the CLCD, refer to the

CLCD registers in the following companion document:

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RM0321: SPEAr320S address map and registers

24.1

Overview

SPEAr320S features a color liquid crystal display controller (CLCD) that provides all the

necessary control signals to interface directly to a variety of color and monochrome LCD

panels.

24.2

Main features

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Compliance to the AMBA specification (Rev 2.0) onwards for easy integration into SoC

implementation

●

Dual 16-deep programmable 32-bit wide FIFOs for buffering incoming display data

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Supports single and dual panel mono super twisted nematic (STN) displays with 4- or

8-bit interfaces

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Supports single and dual panel color and monochrome STN displays

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Supports thin film transistor (TFT) color displays

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Resolution programmable up to 1024 x 768

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15 gray-level mono, 3375 color STN, and 32K color TFT support

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1, 2, or 4 bits-per-pixel (bpp) palettized displays for mono STN

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1, 2, 4 or 8 bpp palettized color displays for color STN and TFT

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16 bits-per-pixel (bpp) true-color non-palettized, for color STN and TFT

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24 bpp true-color non-palettized, for color TFT

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Programmable timing for different display panels

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256-entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM physically frame, line

and pixel clock signals

●

AC bias signal for STN and data enable signal for TFT panels

●

Patented gray scale algorithm

●

Supports little endian, big endian and WindowsCE data formats

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