UPD750064CU datasheet(24/82 Pages) NEC

24 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

Figure 6-1. Clock Generator Block Diagram

XT1

XT2

fXT

Subsystem

clock oscillator

Main system

clock oscillator

HALTNote

STOPNote

WM.3

SCC

SCC3

SCC0

PCC0

PCC1

PCC2

PCC3

PCC2,

PCC3

Clear

STOP F/F

Oscillation

stop

HALT F/F

Wait release signal from BT

RESET signal

Standby release signal from

interrupt control circuit

· CPU

· INT0 noise eliminator

· Clock output circuit

1/4

Divider

1/1 to 1/4096

Divider

1/2 1/4 1/16

· Basic interval timer (BT)

· Timer/event counter

· Serial interface

· Watch timer

· INT0 noise eliminator

· Clock output circuit

PCC

Selector

Watch timer

Note Instruction execution

Remarks 1.

fX = Main system clock frequency

fXT = Subsystem clock frequency

Φ = CPU clock

PCC: Processor Clock Control Register

SCC: System Clock Control Register

One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.

UPD750064CU Datasheet(PDF) 24 Page - NEC

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