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M5-128/192-5VC Datasheet(PDF) 23 Page - Lattice Semiconductor |
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M5-128/192-5VC Datasheet(HTML) 23 Page - Lattice Semiconductor |
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23 / 47 page ![]() MACH 5 Family 23 M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 -5 -6 -7 -10 -12 -15 -20 Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Combinatorial Delay: tPDi Internal combinatorial propagation delay 3.5 4.5 5.5 8.0 10.0 13.0 18.0 ns tPD Combinatorial propagation delay 5.5 6.5 7.5 10.0 12.0 15.0 20.0 ns Registered Delays: tSS Synchronous clock setup time 3.0 3.0 4.0 5.0 6.0 8.0 10.0 ns tSA Asynchronous clock setup time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tHA Asynchronous clock hold time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns tCOSi Synchronous clock to internal output 2.5 3.0 4.0 5.0 6.0 8.0 10.0 ns tCOS Synchronous clock to output 4.5 5.0 6.0 7.0 8.0 10.0 12.0 ns tCOAi Asynchronous clock to internal output 6.0 6.0 8.0 10.0 13.0 15.0 18.0 ns tCOA Asynchronous clock to output 8.0 8.0 10.0 12.0 15.0 17.0 20.0 ns Latched Delays: tSAL Latch setup time 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns tHAL Latch hold time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns tPDLi Transparent latch internal 6.0 7.0 7.0 8.0 9.0 10.0 10.0 ns tPDL Propagation delay through transparent latch 8.0 9.0 9.0 10.0 11.0 12.0 12.0 ns tGOAi Gate to internal output 7.0 8.0 8.0 9.0 10.0 11.0 12.0 ns tGOA Gate to output 9.0 10.0 10.0 11.0 12.0 13.0 14.0 ns Input Register Delays: tSIRS Input register setup time using a synchronous clock 2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns tSIRA Input register setup time using an asynchronous clock 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tHIRS Input register hold time using a synchronous clock 3.0 3.0 3.0 4.0 4.0 4.0 4.0 ns tHIRA Input register hold time using an asynchronous clock 6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns Input Latch Delays: tSIL Input latch setup time 2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns tHIL Input latch hold time 6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns tPDILi Transparent input latch 5.0 5.0 5.5 6.0 6.0 6.0 6.0 ns Output Delays: tBUF Output buffer delay 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns tSLW Slow slew rate delay 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns tEA Output enable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns tER Output disable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns |
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