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M5-128/192-5VC Datasheet(PDF) 25 Page - Lattice Semiconductor

Part # M5-128/192-5VC
Description  Fifth Generation MACH Architecture
PDF  47 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

M5-128/192-5VC Datasheet(HTML) 25 Page - Lattice Semiconductor

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MACH 5 Family
25
Notes:
1. See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site.
2. Numbers in parentheses are for M5-128, M5-192, M5-256.
3. If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (fMAX/2).
Frequency:
fMAX
External feedback, PAL block level. Min
of 1/(tWLS + tWHS) or 1/(tSS + tCOS)
133
125
100
83.3
71.4
55.6
45.5
MHz
Internal feedback, PAL block level. Min
of 1/(tWLS + tWHS) or 1/(tSS +tCOSi)
182
167
125
100
83.3
62.5
50.0
MHz
No feedback PAL block level. Min of
1/(tWLS + tWHS) or 1/(tSS + tHS)
200
167
167
125
100
83.3
83.3
MHz
fMAXA
External feedback, PAL block level. Min
of 1/(tWLA + tWHA) or 1/(tSA + tCOA)
91
91
71.4
58.8
47.6
41.7
35.7
MHz
Internal feedback, PAL block level. Min
of 1/(tWLA + tWHA) or 1/(tSA +tCOAi)
111
111
83.3
66.7
52.6
45.5
38.5
MHz
No feedback, PAL block level. Min of
1/(tWLA + tWHA) or 1/(tSA + tHA)
167
125
125
100
83.3
71.4
62.5
MHz
fMAXI
Maximum input register frequency
1/(tSIRS+tHIRS) or 1/(2 x tWICW)
167
125
125
100
83.3
71.4
62.5
MHz
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-6
-7
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max



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