UPD78C18GF datasheet(45/110 Pages) NEC

45 / 110 page

µPD78C17,78C18

(2)

Synchronous mode

In the synchronous mode, data transfer is performed with 8-bit character length fixed, and with no parity

bit. Therefore, the serial mode register (SML) is set to 0CH (see Fig. 2-26).

Transmission operation is enabled by setting (1) bit 3 (TxE) of the serial mode register (SMH).

If data is written to the transmit buffer by the “MOV TXB, A” instruction and preceding data transfer is

terminated, the contents of the transmit buffer are automatically transferred to the serial register and

converted to serial data, and data starting from LSB are transmitted from TxD at the falling edge of SCK.

The serial data is transferred in the same rate as for SCK.

Data transfer speed in transmission is maximum 500 kbps when an internal clock is used for SCK and

maximum 1 Mbps when an external clock is used (12-MHz operation).

When data is transferred from the transmit buffer to the serial register and the transmit buffer is

empty, the internal interrupt (INTST) is generated.

When TxE is “0” or the serial register has no transmitted data, the TxD pin is in the marking state (1).

Fig. 2-26 Serial Mode Register Format in Synchronous Mode

76543210

0000

1100

SML

Synchronous Operation

Character Length 8-Bit Fixed

Parity Disable

765

43210

RxE

TxE

SK 1

SMH

SCK Selection

External clock

Internal clock (TO output)

Internal clock (

φ384)

Internal clock (

φ24)

Transmission Enable

Reception Enable

Disable

Enable

SK 2

Search Mode

Disable

Enable

Disable

Enable

UPD78C18GF Datasheet(PDF) 45 Page - NEC

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