UPD78C18GF datasheet(65/110 Pages) NEC

65 / 110 page

µPD78C17,78C18

STANDBY FUNCTIONS

Three standby modes are available for the

µPD78C17 and 78C18 to save power consumption in the program

standby mode (the HALT mode, software STOP mode, and hardware STOP mode).

4.1

HALT MODE

When the HLT instruction is executed, the HALT mode is set unless the interrupt request flag of the un-

masked interrupt is set. In the HALT mode the CPU clock stops and program execution also stops. However,

the contents of all registers and internal RAM just before the stoppage are retained. In the HALT mode, the

timer, timer/event counter, serial interface, A/D converter, and interrupt control circuit are operational.

Table 4-1 shows the status of the

µPD78C17 and 78C18 output pins in the HALT mode.

Table 4-1 Output Pin Statuses

Output Pin

Single ChipNote1

External Expansion

PA7 to PA0

Data retained

PB7 to PB0

Data retained

PC7 to PC0

Data retained

PD7 to PD0

Data retained

High-impedance

PF7 to PF0

Data retained

Next address retainedNote2

Data retainedNote3

WR, RD

High-level

ALE

High-level

Notes 1.

µPD78C18 only

2. Address output pin

3. Port data output pin

Caution

Because an interrupt request flag is used to release the HALT mode, HLT instruction execution does

not set the HALT mode if even a single interrupt request flag for an unmasked interrupt is set.

Thus, when setting the HALT mode when there is a possibility that an interrupt request flag may

have been set (when there is a pending interrupt), one of the following procedures should be

followed: First process the pending interrupt; or, reset the interrupt request flag by executing a

skip instruction; or, mask all interrupts except those used to release the HALT mode.

UPD78C18GF Datasheet(PDF) 65 Page - NEC

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