LP28006 datasheet(9/11 Pages) POWER

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Preliminary Datasheet

LP28006

LP28006 – 00 Ver. 1.0 Datasheet

Feb.-2010

www.lowpowersemi.com

Page 9 of 11

Pre- Charge Current Setting During a charge cycle

if the battery voltage is below the VPRECH

threshold, the LP28006 applies a pre-charge mode

to the battery. This feature revives deeply

discharged cell sand protects battery life. The

LP28006 internal determines the pre-charge rate as

10% of the fast-charge current. Battery Voltage

Regulation. The LP28006 monitors the battery

voltage through the BATT pin. Once the battery

voltage level closes to the VREG threshold, the

LP28006 voltage enters constant phase and the

charging current begins to taper down. When

battery voltage is over the VREG threshold, the

LP28006 will stop charge and keep to monitor the

battery voltage. However, when the battery voltage

decreases 100mV below the VREG, it will be

recharged to keep the battery voltage. Charge Status

Outputs. The open-drain CHG_S and PGOOD

outputs indicate various charger operations as

shown in the following table. These status pins can

be used to drive LEDs or communicate to the host

processor. Note that ON indicates the open-drain

transistor is turned on and LED is bright.

Temperature Regulation and Thermal Protection In

order to maximize the charge rate, the LP28006

features a junction temperature regulation loop. If

the power dissipation of the IC results in a junction

temperature greater than the thermal regulation

threshold (125°C), theLP28006 throttles back on the

charge current in order to maintain a junction

temperature around the thermal regulation threshold

(125°C). The LP28006 monitors the junction

temperature, TJ, of the die and disconnects the

battery from the input if TJ exceeds 125°C. This

operation continues until junction temperature falls

below thermal regulation threshold (125°C) by the

hysteresis level. This feature prevents the chip from

damage.

Selecting the Input and Output Capacitors

In most applications, the most important is the

high-frequency decoupling capacitor on the input of

the LP28006.A 1uF ceramic capacitor, placed in

close proximity to input pin and GND pin is

recommended. In some applications depending on

the power supply characteristics and cable length, it

may be necessary to add an additional 10uFceramic

capacitor to the input. The LP28006 requires a small

output capacitor for loop stability. A 1uF ceramic

capacitor placed between the BATT pin and GND is

typically sufficient.

Layout Consideration

The LP28006 is a fully integrated low cost

single-cell Li-Ion battery charger ideal for portable

applications. Careful PCB layout is necessary. For

best performance, place all peripheral components

as close to the IC as possible. A short connection is

highly recommended. The following guide lines

should be strictly followed when designing a PCB

layout for the LP28006.Input capacitor should be

placed close to IC and connected to ground plane.

The trace of input in the PCB should be placed far

away the sensitive devices or shielded by the

ground.

The GND should be connected to a strong ground

plane for heat sinking and noise protection. The

connection of RSETA should be isolated from other

noisy traces. The short wire is recommended to

prevent EMI and noise coupling. Output capacitor

should be placed close to IC and connected to

ground plane to reduce noise coupling. The TS's

capacitor should be placed close to TS (Pin 9) and

connected to ground plane. The capacitance (0.1uF

to10uF) base on PCB layout. When PCB has poor

layout, the 10uF is recommended to prevent noise.

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