STC5428 datasheet(13/66 Pages) CONNOR-WINFIELD

13 / 66 page

Page 13 of 66

Rev: 0.2

Date: April 3, 2014

STC5428

Synchronous Clock for SETS

DATASHEET

Preliminary

Note 6: Timing generator T0 and T4 share register 0x20 ~ 0x3F. Register 0x1F selects between T0 and T4 for the sharing registers 0x20

~0x3F.

0x4B

Synth_Freq_Value

17-0

R/W

Selects synthesizer frequency value from 1MHz to 156.25MHz, in

1kHz steps, based on which synthesizer index is selected at the reg-

ister Synth_Index_Select

0x4C

0x4D

0x4E

Synth_Skew_Adj

11-0

R/W

Adjust phase skew for the synthesizer with the index selected at

0x4F

0x50

CLK1/2_Signal_Level

1-0

R/W

Select the signal level (LVDS or LVPECL) for clock outputs CLK1

and CLK2

0x51

CLK1_Sel

1-0

R/W

Select synthesizer or enable tri-state for CLK1

0x52

CLK2_Sel

1-0

R/W

Select synthesizer or enable tri-state for CLK2

0x53

CLK3_Sel

1-0

R/W

Select synthesizer or enable tri-state for CLK3

0x54

CLK4_Sel

1-0

R/W

Select synthesizer or enable tri-state for CLK4

0x55

CLK5_Sel

1-0

R/W

Select synthesizer or enable tri-state for CLK5

0x56

CLK6_Sel

1-0

R/W

Select synthesizer or enable tri-state for CLK6

0x57

CLK7_Sel

1-0

R/W

Select synthesizer or enable tri-state for CLK7

0x58

CLK8_Sel

1-0

R/W

Select synthesizer or enable tri-state for CLK8

0x59

Frame8K_Sel

6-0

R/W

8kHz frame pulse clock duty cycle selection, signal inversion

0x5A

Frame2K_Sel

6-0

R/W

2kHz frame pulse clock duty cycle selection, signal inversion

0x5B

Ref_Acceptable_Freq

14-0

R/W

Select integer N for manually acceptable frequency at Nx8kHz;

Enable auto detection of reference input frequency

0x5C

0x5D

Frame_Mux

11-0

R/W

Select one of frame signal (Frame8K, Frame2K, or composite sig-

nal) and forward it to CLK3~CLK8 selection individually

0x5E

0x5F

Diff_REF_Polarity

1-0

R/W

Differential input REF(11~12)_P and REF(11~12)_N polarity reverse

0x70

Field_Upgrade_Status

2-0

Indicates the status of field upgrade process

0x71

Field_Upgrade_Data

7-0

R/W

Load 7600 bytes of firmware configuration data

0x72

Field_Upgrade_Count

12-0

Count byte numbers that have been loaded

0x73

0x74

Field_Upgrade_Start

7-0

Write three values consecutively to start the field upgrade process

0x7F

MCLK_Freq_Reset

7-0

R/W

Select the frequency of the external oscillator

Table 5: Register Map

Addr

Reg Name

Bits

Type

Description

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