STC5428 datasheet(39/66 Pages) CONNOR-WINFIELD

39 / 66 page

Page 39 of 66

Rev: 0.2

Date: April 3, 2014

STC5428

Synchronous Clock for SETS

DATASHEET

Preliminary

Event1: Cross reference activity status

0 = no change, 1 = cross reference activity status changed.

Event2: T0 selected reference in auto-selection mode

0= no change, 1 = T0 selected reference changed

Event3: T0 PLL status

0= no change, 1 = T0 PLL status changed

Event4: T0 timing generator’s event out

0= no event out, 1= any of T0 PLL event out is asserted or not cleared at the register of

PLL_Event_Out

Event5: T4 selected reference in auto-selection mode

0= no change, 1 = T4 selected reference changed

Event6: T4 PLL status

0= no change, 1 = T0 PLL status changed

Event7: T4 timing generator’s event out

0= no event out, 1= any of T4 PLL event out is asserted or not cleared at the register of

PLL_Event_Out

Interrupts are cleared by writing “1” to the bit positions

Default value: 0

Interrupt_Event_Mask, 0x1B (R/W)

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x1B

Event 7

Event 6

Event 5

Event 4

Event 3

Event 2

Event 1

Event 0

Selects which of events will assert the pin EVENT_INTR to active mode (See register Interrupt_Config).

0 = mask out, 1 = enable

Default value: 0

Interrupt_Config, 0x1C (R/W)

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x1C

Not used

Idle mode

Active sig-

nal level

Active signal level

Sets the signal level in active mode.

0 = active low. 1 = active high

Idle mode

Specify the state of pin EVENT_INTR when no interrupt event occurs.

0 = tri-state. 1 = logic inactive

Default value: 0

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