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ICS8530-01 Datasheet(PDF) 1 Page - Integrated Device Technology |
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ICS8530-01 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 17 page  DATA SHEET ICS8530FY-01 REVISION G NOVEMBER 15, 2012 1 ©2012 Integrated Device Technology, Inc. Low Skew, 1-to16, Differential-to-3.3V LVPECL Fanout Buffer ICS8530-01 General Description The ICS8530-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV as long as the common mode voltage is within the specified minimum and maximum range. Guaranteed output and part-to-part skew characteristics make the ICS8530-01 ideal for those clock distribution applications demanding well defined performance and repeatability. Features • Sixteen differential 3.3V LVPECL outputs • CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 500MHz • Translates any single-ended input signal to 3.3V LVPECL levels with a resistor bias on nCLK input • Output skew: 75ps (maximum) • Part-to-part skew: 305ps (maximum) • Additive phase jitter, RMS: 0.03ps (typical) • Full 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 VCCO Q11 nQ11 Q10 nQ10 VEE Q9 nQ9 Q8 nQ8 VCCO VCC CLK VCCO nQ0 Q0 nQ1 Q1 VEE nQ2 Q2 nQ3 Q3 VCCO 48 47 46 45 44 43 42 41 40 39 38 37 Pulldown Pullup Q15 nQ15 CLK nCLK Q14 Q13 Q12 nQ14 nQ13 nQ12 Q11 nQ11 Q10 Q9 Q8 nQ10 nQ9 nQ8 Q0 nQ0 Q1 Q2 Q3 nQ1 nQ2 nQ3 Q4 nQ4 Q5 Q6 Q7 nQ5 nQ6 nQ7 Block Diagram Pin Assignment ICS8530-01 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View |
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