89HPES10T4G2 datasheet(6/30 Pages) IDT

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August 10, 2011

IDT 89HPES10T4G2 Data Sheet

Signal

Type

Name/Description

CCLKDS

Common Clock Downstream. The assertion of this pin indicates that all

downstream ports are using the same clock source as that provided to

downstream devices.This bit is used as the initial value of the Slot Clock

Configuration bit in all of the Link Status Registers for downstream ports.

The value may be overridden by modifying the SCLK bit in each down-

stream port’s PCIELSTS register.

CCLKUS

Common Clock Upstream. The assertion of this pin indicates that the

upstream port is using the same clock source as the upstream device. This

bit is used as the initial value of the Slot Clock Configuration bit in the Link

Status Register for the upstream port. The value may be overridden by

modifying the SCLK bit in the P0_PCIELSTS register.

MSMBSMODE

Master SMBus Slow Mode. The assertion of this pin indicates that the

master SMBus should operate at 100 KHz instead of 400 KHz. This value

may not be overridden.

PERSTN

Fundamental Reset. Assertion of this signal resets all logic inside

PES10T4G2 and initiates a PCI Express fundamental reset.

RSTHALT

Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, PES10T4G2 executes the reset procedure and remains in a reset

state with the Master and Slave SMBuses active. This allows software to

read and write registers internal to the device before normal device opera-

tion begins. The device exits the reset state when the RSTHALT bit is

cleared in the SWCTL register by an SMBus master.

SWMODE[2:0]

Switch Mode. These configuration pins determine the PES10T4G2 switch

operating mode.

0x0 - Normal switch mode

0x1 - Normal switch mode with Serial EEPROM initialization

0x2 - through 0x7 Reserved

These pins should be static and not change following the negation of

PERSTN.

Table 5 System Pins

Signal

Type

Name/Description

JTAG_TCK

JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is

independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI

JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

Table 6 Test Pins (Part 1 of 2)

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