LMP92001

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SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012

In the expression above VREF is the reference voltage input to the internal ADC. VREF can be either externally

applied at the AREF pin of the device, or be internally generated.

Sampling Transient

An instantaneous current will flow at the beginning of TRACK period which may lead to temporary disturbance of

the input potential. This current, and resulting disturbance, will vary with the magnitude of the sampled signal and

source impedance ROUT.

Channel Selection

The analog input channels are enabled by setting corresponding enable bits ENx in the control registers CAD1,

CAD2, and CAD3. Enabling of the channels does not begin the conversion process.

Single-Shot and Continuous Sequencing

The ADC is in the idle state until either the Single-Shot or Continuous conversion is initiated. The channels

whose corresponding ENx bit in the CAD(1|2|3) registers is set will be sampled and converted by the ADC.

Single-Shot conversion begins when the user performs a write operation ( 0 or 1 ) to CTRIG.SNGL while

CGEN.STRT=0. Once the sequence is completed the ADC returns to the idle state.

Continuous conversion begins when the user sets the CGEN.STRT bit. The sequencing of events is the same as

in the Single Mode. Upon completing the sequence of conversions another sequence is automatically started.

This process will continue until the user clears the CGEN.STRT bit.

The operation of the Analog Sense Subsystem is further illustrated in Figure 15.

Copyright © 2011–2012, Texas Instruments Incorporated

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