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SY100S331JC Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100S331JC Datasheet(HTML) 1 Page - Micrel Semiconductor |
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1 / 7 page  TRIPLE D FLIP-FLOP SY100S331 s Max. toggle frequency of 800MHz s Differential outputs s IEE min. of –80mA s Industry standard 100K ECL levels s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75K Ω input pull-down resistors s 150% faster than Fairchild s 40% lower power than Fairchild s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages FEATURES DESCRIPTION The SY100S331 offers three D-type, edge-triggered master/slave flip-flops with true and complement outputs, designed for use in high-performance ECL systems. Each flip-flop is controlled by a common clock (CPc), as well as its own clock pulse (CPn). The resultant clock signal controlling the flip-flop is the logical OR operation of these two clock signals. Data enters the master when both CPc and CPn are LOW and enters the slave on the rising edge of either CPc or CPn (or both). Additional control signals include Master Set (MS) and Master Reset (MR) inputs. Each flip-flop also has its own Direct Set (SDn) and Direct Clear (CDn) signals. The MR, MS, SDn and DCn signals override the clock signals. The inputs on this device have 75K Ω pull-down resistors. Rev.: G Amendment: /0 Issue Date: July, 1999 BLOCK DIAGRAM CPC CP D SD CD CP2 CD2 D2 SD2 Q2 Q2 CP D SD CD CP1 CD1 D1 SD1 Q1 Q1 CP D SD CD CP0 CD0 D0 SD0 Q0 Q0 MS MR SD0 CD0 CP0 D0 Q0 Q0 CP1 SD2 CP2 CD1 D2 CD2 18 17 16 15 14 13 1 2 3 4 5 6 7 24 8 23 9 22 10 21 11 20 12 19 Top View Flatpack F24-1 PIN CONFIGURATIONS Q1 Q1 VCCA VCC Q2 VCC MS VEE MR CPC SD1 VEES 4 3 2 1 28 27 12 13 14 15 16 17 19 11 20 10 21 9 22 8 23 7 24 6 Top View PLCC J28-1 Q2 D1 26 18 25 5 1 |
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