24LCS21

DS21127B-page 6

© 1996 Microchip Technology Inc.

3.1.4

DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last

eight will be stored when doing a write operation. When

an overwrite does occur it will replace data in a first in

first out fashion.

Note:

Once switched into bi-directional Mode,

the 24LCS21 will remain in that mode until

power goes away. Removing power is the

only way to reset the 24LCS21 into the

Transmit-only mode.

3.1.5

ACKNOWLEDGE

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse.

Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

Note:

The 24LCS21 does not generate any

acknowledge

bits

if

an

internal

programming cycle is in progress.

FIGURE 3-3: BUS TIMING START/STOP

FIGURE 3-4: BUS TIMING DATA

START

STOP

SCL

SDA

SCL

SDA

IN

SDA

OUT