PIC16F87X datasheet(25/218 Pages) MICROCHIP

25 / 218 page

 2001 Microchip Technology Inc.

DS30292C-page 23

PIC16F87X

2.2.2.6

PIE2 Register

The PIE2 register contains the individual enable bits for

the CCP2 peripheral interrupt, the SSP bus collision

interrupt, and the EEPROM write operation interrupt.

PIE2 REGISTER (ADDRESS 8Dh)

U-0

R/W-0

U-0

R/W-0

U-0

R/W-0

—

Reserved

—

EEIE

BCLIE

—

CCP2IE

bit 7

bit 0

bit 7

Unimplemented: Read as '0'

bit 6

Reserved: Always maintain this bit clear

bit 5

Unimplemented: Read as '0'

bit 4

EEIE: EEPROM Write Operation Interrupt Enable

= Enable EE Write Interrupt

= Disable EE Write Interrupt

bit 3

BCLIE: Bus Collision Interrupt Enable

= Enable Bus Collision Interrupt

= Disable Bus Collision Interrupt

bit 2-1

Unimplemented: Read as '0'

bit 0

CCP2IE: CCP2 Interrupt Enable bit

= Enables the CCP2 interrupt

= Disables the CCP2 interrupt

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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