PIC16F87X datasheet(49/218 Pages) MICROCHIP

49 / 218 page

 2001 Microchip Technology Inc.

DS30292C-page 47

PIC16F87X

5.0

TIMER0 MODULE

The Timer0 module timer/counter has the following fea-

tures:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 5-1 is a block diagram of the Timer0 module and

the prescaler shared with the WDT.

Additional information on the Timer0 module is avail-

able in the PICmicro™ Mid-Range MCU Family Refer-

ence Manual (DS33023).

Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In Timer mode, the Timer0 mod-

ule will increment every instruction cycle (without pres-

caler). If the TMR0 register is written, the increment is

inhibited for the following two instruction cycles. The

user can work around this by writing an adjusted value

to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION_REG<5>). In Counter mode, Timer0 will

increment either on every rising, or falling edge of pin

RA4/T0CKI. The incrementing edge is determined by

the

Timer0

Source

Edge

Select

bit,

T0SE

(OPTION_REG<4>). Clearing bit T0SE selects the ris-

ing edge. Restrictions on the external clock input are

discussed in detail in Section 5.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. The pres-

caler is not readable or writable. Section 5.3 details the

operation of the prescaler.

5.1

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in software by the Timer0 module Interrupt Ser-

vice Routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP, since the timer is shut-off during SLEEP.

FIGURE 5-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

RA4/T0CKI

T0SE

CLKOUT (= FOSC/4)

SYNC

Cycles

TMR0 Reg

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

WDT Enable bit

Data Bus

Set Flag Bit T0IF

on Overflow

PSA

T0CS

PRESCALER

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