| Electronic Components Datasheet Search |
|
PIC17C752-08/P Datasheet(PDF) 93 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC17C752-08/P Datasheet(HTML) 93 Page - Microchip Technology |
|
93 / 320 page ![]() © 1997 Microchip Technology Inc. Preliminary DS30264A-page 93 PIC17C75X FIGURE 13-3: TCON3 REGISTER (ADDRESS: 16h, BANK 7) U-0 R - 0 R - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 - CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON R = Readable bit W = Writable bit U = Unimplemented bit, Reads as ‘0’ -n = Value at POR reset bit7 bit0 bit 7: Unimplemented: Read as ‘0’ bit 6: CA4OVF: Capture4 Overflow Status bit This bit indicates that the capture value had not been read from the capture register pair (CA4H:CA4L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overflow). Subsequent capture events will not update the capture register with the TMR3 value until the capture register has been read (both bytes). 1 = Overflow occurred on Capture4 registers 0 = No overflow occurred on Capture4 registers bit 5: CA3OVF: Capture3 Overflow Status bit This bit indicates that the capture value had not been read from the capture register pair (CA3H:CA3L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overflow). Subsequent capture events will not update the capture register with the TMR3 value until the capture register has been read (both bytes). 1 = Overflow occurred on Capture3 registers 0 = No overflow occurred on Capture3 registers bit 4-3: CA4ED1:CA4ED0: Capture4 Mode Select bits 00 = Capture on every falling edge 01 = Capture on every rising edge 10 = Capture on every 4th rising edge 11 = Capture on every 16th rising edge bit 2-1: CA3ED1:CA3ED0: Capture3 Mode Select bits 00 = Capture on every falling edge 01 = Capture on every rising edge 10 = Capture on every 4th rising edge 11 = Capture on every 16th rising edge bit 0: PWM3ON: PWM3 On bit 1 = PWM3 is enabled (The RG5/PWM3 pin ignores the state of the DDRG<5> bit) 0 = PWM3 is disabled (The RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |