PIC17C752-08SLASHP datasheet(102/320 Pages) MICROCHIP

102 / 320 page

PIC17C75X

DS30264A-page 102

Preliminary

13.2.2

FOUR CAPTURE MODE

This mode is selected by setting bit CA1/PR3. A block

diagram is shown in Figure 13-9. In this mode, TMR3

runs without a period register and increments from

0000h to FFFFh and rolls over to 0000h. The TMR3

interrupt Flag (TMR3IF) is set on this rollover. The

TMR3IF bit must be cleared in software.

Registers PR3H/CA1H and PR3L/CA1L make a 16-bit

capture register (Capture1). It captures events on pin

RB0/CAP1. Capture mode is conﬁgured by the

CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit

(CA1IF) is set upon detection of the capture event. The

corresponding interrupt mask bit is CA1IE. The

Capture1 Overﬂow Status bit is CA1OVF.

All the captures operate in the same manner. Refer to

Section 13.2.1 for the operation of capture.

FIGURE 13-9: TIMER3 WITH FOUR CAPTURES BLOCK DIAGRAM

RB0/CAP1

Edge Select,

Prescaler Select

PR3H/CA1H

PR3L/CA1L

RB1/CAP2

RG4/CAP3

Edge Select,

Prescaler Select

Set CA1IF

(PIR1<2>)

Capture1 Enable

TMR3ON

TMR3CS

(TCON1<2>)

Set TMR3IF

(PIR1<6>)

Edge Select,

Prescaler Select

CA2H

CA2L

Set CA2IF

(PIR1<3>)

CA3H

CA3L

Set CA3IF

(PIR2<2>)

CA1ED1, CA1ED0

(TCON1<5:4>)

(TCON2<2>)

Fosc/4

RB5/TCLK3

Capture2 Enable

Capture3 Enable

CA2ED1, CA2ED0

(TCON1<7:6>)

CA3ED1: CA3ED0

(TCON3<2:1>)

TMR3H

TMR3L

RE3/CAP4

Edge Select,

Prescaler Select

CA4H

CA4L

Set CA4IF

(PIR2<3>)

Capture4 Enable

CA4ED1: CA4ED0

(TCON3<4:3>)

PIC17C752-08/P Datasheet(PDF) 102 Page - Microchip Technology

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