PIC17C752-08SLASHP datasheet(134/320 Pages) MICROCHIP

134 / 320 page

PIC17C75X

DS30264A-page 134

Preliminary

15.2 SSP I2C Operation

The SSP module in I2C mode fully implements all mas-

ter and slave functions (including general call support)

and provides interrupts on start and stop bits in hard-

ware to determine a free bus (multi-master function).

The SSP module implements the standard mode spec-

iﬁcations as well as 7-bit and 10-bit addressing.

Appendix E gives an overview of the I2C bus speciﬁca-

tion.

FIGURE 15-13: SSP BLOCK DIAGRAM

(I2C MODE)

FIGURE 15-14: I2C MASTER MODE BLOCK

DIAGRAM

Read

Write

SSPSR reg

Match detect

SSPADD reg

Start and

Stop bit detect

SSPBUF reg

Internal

data bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

SCL

shift

clock

MSb

LSb

SDA

Read

Write

SSPSR reg

Match detect

SSPADD reg

Start and Stop bit

detect / generate

SSPBUF reg

Internal

data bus

Addr Match

Set/Clear S bit

Clear/Set P, bits

(SSPSTAT reg)

SCL

shift

clock

MSb

LSb

SDA

Baud Rate Generator

SSPADD<6:0>

and

and Set SSPIF

Two pins are used for data transfer. These are the SCL

pin, which is the clock, and the SDA pin, which is the

data. Pins that are on PortA are automatically conﬁg-

ured when the I2C mode is enabled. The SSP module

functions are enabled by setting SSP Enable bit

SSPEN (SSPCON1<5>).

The SSP module has six registers for I2C operation.

These are the:

• SSP Control Register1 (SSPCON1)

• SSP Control Register2 (SSPCON2)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly acces-

sible

• SSP Address Register (SSPADD)

The SSPCON1 register allows control of the I2C oper-

ation. Four mode selection bits (SSPCON1<3:0>)

allow one of the following I2C modes to be selected:

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

•I2C Master mode, clock = OSC/4 (SSPADD +1)

Selection of any I2C mode, with the SSPEN bit set,

forces the SCL and SDA pins to be open drain. These

pins are on PORTA and therefore there is no need to

program to be inputs.

The SSPSTAT register gives the status of the data

transfer. This information includes detection of a

START or STOP bit, speciﬁes if the received byte was

data or address if the next byte is the completion of

10-bit address, and if this will be a read or write data

transfer.

The SSPBUF is the register to which transfer data is

written to or read from. The SSPSR register shifts the

data in or out of the device. In receive operations, the

SSPBUF and SSPSR create a doubled buffered

receiver. This allows reception of the next byte to begin

before reading the last byte of received data. When the

complete byte is received, it is transferred to the

SSPBUF register and ﬂag bit SSPIF is set. If another

complete byte is received before the SSPBUF register

is read, a receiver overﬂow has occurred and bit

SSPOV (SSPCON1<6>) is set and the byte in the

SSPSR is lost.

The SSPADD register holds the slave address. In

10-bit mode, the user needs to write the high byte of the

address (1111 0 A9 A8 0). Following the high byte

address match, the low byte of the address needs to be

loaded (A7:A0).

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