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PIC17C752-08/CL Datasheet(PDF) 263 Page - Microchip Technology |
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PIC17C752-08/CL Datasheet(HTML) 263 Page - Microchip Technology |
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263 / 328 page  © 1998 Microchip Technology Inc. Preliminary DS30289A-page 263 PIC17C7XX FIGURE 20-21: MEMORY INTERFACE READ TIMING TABLE 20-22: MEMORY INTERFACE READ REQUIREMENTS Param. No. Sym Characteristic Min Typ† Max Units Conditions 150 TadV2alL AD15:AD0 (address) valid to PIC17CXXX 0.25TCY - 10 — — ns ALE ↓ (address setup time) PIC17LCXXX 0.25TCY - 10* — — 151 TalL2adI ALE ↓ to address out invalid PIC17CXXX 5* — — ns (address hold time) PIC17LCXXX 5* — — 160 TadZ2oeL AD15:AD0 hi-impedance to PIC17CXXX 0* — — ns OE ↓ PIC17LCXXX 0* — — 161 ToeH2adD OE ↑ to AD15:AD0 driven PIC17CXXX 0.25TCY - 15 — — ns PIC17LCXXX 0.25TCY - 15* — — 162 TadV2oeH Data in valid before OE ↑ PIC17CXXX 35 — — ns (data setup time) PIC17LCXXX 45* — — 163 ToeH2adI OE ↑to data in invalid PIC17CXXX 0 — — ns (data hold time) PIC17LCXXX 0* — — 164 TalH ALE pulse width PIC17CXXX — 0.25TCY §— ns PIC17LCXXX — 0.25TCY §— 165 ToeL OE pulse width PIC17CXXX 0.5TCY - 35 § — — ns PIC17LCXXX 0.5TCY - 35 § — — 166 TalH2alH ALE ↑ to ALE↑(cycle time) PIC17CXXX — TCY §— ns PIC17LCXXX — TCY §— 167 Tacc Address access time PIC17CXXX — — 0.75TCY - 30 ns PIC17LCXXX — — 0.75TCY - 45* 168 Toe Output enable access time PIC17CXXX — — 0.5TCY - 45 ns (OE low to Data Valid) PIC17LCXXX — — 0.5TCY - 75* * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. OSC1 ALE OE AD<15:0> WR Q1 Q2 Q3 Data in Addr out 150 151 160 166 165 162 163 161 '1' '1' Q4 Q1 Q2 Addr out 164 168 167 |
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