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PIC17C752-08/CL Datasheet(PDF) 260 Page - Microchip Technology

Part # PIC17C752-08/CL
Description  High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
PDF  328 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC17C752-08/CL Datasheet(HTML) 260 Page - Microchip Technology

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PIC17C7XX
DS30289A-page 260
Preliminary
© 1998 Microchip Technology Inc.
TABLE 20-19: A/D CONVERTER CHARACTERISTICS
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
10
bit
VREF+ = VDD = 5.12V,
VSS
≤ VAIN ≤ VREF+
—
—
10*
bit
(VREF+ — VREF-)
≥ 3.0V,
VREF-
≤ VAIN ≤ VREF+
A02
EABS
Absolute error
—
—
<
±1
LSb
VREF+ = VDD = 5.12V,
VSS
≤ VAIN ≤ VREF+
—
—
<
±1*
LSb
(VREF+ — VREF-)
≥ 3.0V,
VREF-
≤ VAIN ≤ VREF+
A03
EIL
Integral linearity error
—
—
<
±1
LSb
VREF+ = VDD = 5.12V,
VSS
≤ VAIN ≤ VREF+
—
—
<
±1*
LSb
(VREF+ — VREF-)
≥ 3.0V,
VREF-
≤ VAIN ≤ VREF+
A04
EDL
Differential linearity error
—
—
<
±1
LSb
VREF+ = VDD = 5.12V,
VSS
≤ VAIN ≤ VREF+
—
—
<
±1*
LSb
(VREF+ — VREF-)
≥ 3.0V,
VREF-
≤ VAIN ≤ VREF+
A05
EFS
Full scale error
—
—
<
±1
LSb
VREF+ = VDD = 5.12V,
VSS
≤ VAIN ≤ VREF+
—
—
<
±1*
LSb
(VREF+ — VREF-)
≥ 3.0V,
VREF-
≤ VAIN ≤ VREF+
A06
EOFF
Offset error
—
—
<
±1
LSb
VREF+ = VDD = 5.12V,
VSS
≤ VAIN ≤ VREF+
—
—
<
±1*
LSb
(VREF+ — VREF-)
≥ 3.0V,
VREF-
≤ VAIN ≤ VREF+
A10
—
Monotonicity
—
guaran-
teed
——
VSS
≤ VAIN ≤ VREF
A20
VREF
Reference voltage
(VREF+ — VREF-)
0V
—
—
V
VREF delta when changing voltage lev-
els on VREF inputs.
A20A
3V *
—
—
V
Absolute minimum electrical spec.
To ensure 10-bit accuracy
A21
VREF+
Reference voltage High
AVSS
+ 3.0V
—AVDD +
0.3V
V
A22
VREF-
Reference voltage Low
AVSS
- 0.3V
—AVDD -
3.0V
V
A25
VAIN
Analog input voltage
AVSS
- 0.3V
—VREF +
0.3V
V
A30
ZAIN
Recommended impedance of
analog voltage source
—
—
10.0
k
Ω
A40
IAD
A/D conversion
current (VDD)
PIC17CXXX
—
180
—
µA
Average current consumption when
A/D is on. (Note 1)
PIC17LCXXX
—
90
—
µA
A50
IREF
VREF input current (Note 2)
10
—
1000
µA
During VAIN acquisition.
Based on differential of VHOLD to VAIN.
——
10
µA
During A/D conversion cycle
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25
°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1:
When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2:
VREF current is from RG0 and RG1 pins or AVDD and AVSS pins, whichever is selected as reference input.



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