PIC17C752-08SLASHCL datasheet(257/328 Pages) MICROCHIP

257 / 328 page

Preliminary

DS30289A-page 257

PIC17C7XX

FIGURE 20-14: I2C BUS DATA TIMING

TABLE 20-14: I2C BUS DATA REQUIREMENTS

Param No.

Sym

Characteristic

Min

Max

Units

Conditions

100

THIGH

Clock high time

100 kHz mode

2(TOSC)(BRG + 1) §

—

400 kHz mode

2(TOSC)(BRG + 1) §

—

1 MHz mode (1)

2(TOSC)(BRG + 1) §

—

101

TLOW

Clock low time

100 kHz mode

2(TOSC)(BRG + 1) §

—

400 kHz mode

2(TOSC)(BRG + 1) §

—

1 MHz mode (1)

2(TOSC)(BRG + 1) §

—

102

SDA and SCL

rise time

100 kHz mode

—

1000 *

Cb is speciﬁed to be from

10 to 400 pF

400 kHz mode

20 + 0.1Cb *

300 *

1 MHz mode (1)

—

300 *

103

SDA and SCL

fall time

100 kHz mode

—

300 *

Cb is speciﬁed to be from

10 to 400 pF

400 kHz mode

20 + 0.1Cb *

300 *

1 MHz mode (1)

—

100 *

TSU:STA

START condition

setup time

100 kHz mode

2(TOSC)(BRG + 1) §

—

Only relevant for repeated

START condition

400 kHz mode

2(TOSC)(BRG + 1) §

—

1 MHz mode (1)

2(TOSC)(BRG + 1) §

—

THD:STA

START condition

hold time

100 kHz mode

2(TOSC)(BRG + 1) §

—

After this period the ﬁrst

clock pulse is generated

400 kHz mode

2(TOSC)(BRG + 1) §

—

1 MHz mode (1)

2(TOSC)(BRG + 1) §

—

106

THD:DAT

Data input

hold time

100 kHz mode

—

400 kHz mode

0.9 *

1 MHz mode (1)

TBD *

—

107

TSU:DAT

Data input

setup time

100 kHz mode

250 *

—

Note 2

400 kHz mode

100 *

—

1 MHz mode (1)

TBD *

—

TSU:STO

STOP condition

setup time

100 kHz mode

2(TOSC)(BRG + 1) §

—

400 kHz mode

2(TOSC)(BRG + 1) §

—

1 MHz mode (1)

2(TOSC)(BRG + 1) §

—

109

TAA

Output valid

from clock

100 kHz mode

—

3500 *

400 kHz mode

—

1000 *

1 MHz mode (1)

——

110

TBUF

Bus free time

100 kHz mode

4.7 ‡

—

Time the bus must be free

before a new transmission

can start

400 kHz mode

1.3 ‡

—

1 MHz mode (1)

TBD *

—

D102 ‡

Bus capacitive loading

—

400 *

Characterized but not tested.

This speciﬁcation ensured by design.

‡

These parameters are for design guidance only and are not tested, nor characterized.

Note 1:

Maximum pin capacitance = 10 pF for all I2C pins.

A fast-mode (400 KHz) I2C-bus device can be used in a standard-mode I2C-bus system, but the parameter # 107

≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.

Parameter # 102 + # 107 = 1000 + 250 = 1250 ns (for 100 kHz-mode) before the SCL line is released.

Cb is speciﬁed to be from 10-400pF. The minimum speciﬁcations are characterized with Cb=10pF. The rise time spec (tr)

is characterized with Rp=Rp min. The minimum fall time speciﬁcation (tf) is characterized with Cb=10pF, and Rp=Rp max.

These are only valid for fast mode operation (VDD=4.5-5.5V) and where the SPM bit (SSPSTAT<7>)=1.)

Max speciﬁcations for these parameters are valid for falling edge only. Specs are characterized with Rp=Rp min and

Cb=400pF for standard mode, 200pF for fast mode, and 10pF for 1MHz mode.

Note: Refer to Figure 20-1 for load conditions.

100

101

103

106

107

109

110

102

SCL

SDA

Out

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