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PIC17C752-08/CL Datasheet(PDF) 261 Page - Microchip Technology |
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PIC17C752-08/CL Datasheet(HTML) 261 Page - Microchip Technology |
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261 / 328 page ![]() © 1998 Microchip Technology Inc. Preliminary DS30289A-page 261 PIC17C7XX FIGURE 20-19: A/D CONVERSION TIMING TABLE 20-20: A/D CONVERSION REQUIREMENTS Param. No. Sym Characteristic Min Typ† Max Units Conditions 130 TAD A/D clock period PIC17CXXX 1.6 — — µs TOSC based, VREF ≥ 3.0V PIC17LCXXX 3.0 — — µsTOSC based, VREF full range PIC17CXXX 2.0 * 4.0 6.0 * µs A/D RC Mode PIC17LCXXX 3.0 * 6.0 9.0 * µs A/D RC Mode 131 TCNV Conversion time (not including acquisition time) (Note 1) 11 § — 12 § TAD 132 TACQ Acquisition time (Note 2) 10 * 20 — — — µs µs The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1LSb (i.e. 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to ADCLK start — Tosc/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be exe- cuted. * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25 °C unless otherwise stated. Parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 131 130 132 BSF ADCON0, GO Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE OLD_DATA SAMPLING STOPPED DONE NEW_DATA (TOSC/2) (1) 98 7 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1 TCY . . . . . . |
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