Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

PIC17C752-08/CL Datasheet(PDF) 258 Page - Microchip Technology

Part # PIC17C752-08/CL
Description  High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
PDF  328 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC17C752-08/CL Datasheet(HTML) 258 Page - Microchip Technology

Back Button PIC17C752-08/CL Datasheet HTML 254Page - Microchip Technology PIC17C752-08/CL Datasheet HTML 255Page - Microchip Technology PIC17C752-08/CL Datasheet HTML 256Page - Microchip Technology PIC17C752-08/CL Datasheet HTML 257Page - Microchip Technology PIC17C752-08/CL Datasheet HTML 258Page - Microchip Technology PIC17C752-08/CL Datasheet HTML 259Page - Microchip Technology PIC17C752-08/CL Datasheet HTML 260Page - Microchip Technology PIC17C752-08/CL Datasheet HTML 261Page - Microchip Technology PIC17C752-08/CL Datasheet HTML 262Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 258 / 328 page
background image
PIC17C7XX
DS30289A-page 258
Preliminary
© 1998 Microchip Technology Inc.
FIGURE 20-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 20-15: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 20-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 20-16: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ
†
Max
Units
Conditions
120
TckH2dtV
SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
PIC17CXXX
—
—
50
ns
PIC17LCXXX
—
—
75 *
ns
121
TckRF
Clock out rise time and fall
time (Master Mode)
PIC17CXXX
—
—
25
ns
PIC17LCXXX
—
—
40 *
ns
122
TdtRF
Data out rise time and fall time
PIC17CXXX
—
—
25
ns
PIC17LCXXX
—
—
40 *
ns
*
Characterized but not tested.
†
Data in “Typ” column is at 5V, 25
∞C unless otherwise stated.These parameters are for design guidance only and are
not tested.
Param
No.
Sym
Characteristic
Min
Typ
†
Max
Units
Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data setup before CK
↓ (DT setup time)
15
—
—
ns
126
TckL2dtl
Data hold after CK
↓ (DT hold time)
15
—
—
ns
†
Data in “Typ” column is at 5V, 25
°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
121
121
120
122
TX/CK
RX/DT
pin
pin
125
126
TX/CK
RX/DT
pin
pin



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com