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PIC16F628-20/SS Datasheet(PDF) 15 Page - Microchip Technology |
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PIC16F628-20/SS Datasheet(HTML) 15 Page - Microchip Technology |
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15 / 160 page  © 1999 Microchip Technology Inc. Preliminary DS40300B-page 15 PIC16F62X 4.2.2 SPECIAL FUNCTION REGISTERS The special function registers are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-1). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. TABLE 4-1: SPECIAL REGISTERS SUMMARY BANK0 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other Resets(1) Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 xxxx 0000 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h Unimplemented — — 08h Unimplemented — — 09h Unimplemented — — 0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 0Dh Unimplemented — — 0Eh TMR1L Holding register for the least significant byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the most significant byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 TMR2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -uuu uuuu 13h Unimplemented — — 14h Unimplemented — — 15h CCPR1L Capture/Compare/PWM register (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit data register 0000 0000 0000 0000 1Ah RCREG USART Receive data register 0000 0000 0000 0000 1Bh Unimplemented — — 1Ch Unimplemented — — 1Dh Unimplemented — — 1Eh Unimplemented — — 1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation. |
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