LM20136

SNVS564B – JANUARY 2009 – REVISED APRIL 2013

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Soft-Start and Voltage Tracking

The SS/TRK pin is a dual function pin that can be used to set the start up time or track an external voltage

source. The start up or Soft-Start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground.

The Soft-Start feature allows the regulator output to gradually reach the steady state operating point, thus

reducing stresses on the input supply and controlling start up current. If no Soft-Start capacitor is used the device

defaults to the internal Soft-Start circuitry resulting in a start up time of approximately 1ms. For applications that

require a monotonic start up or utilize the PGOOD pin, an external Soft-Start capacitor is recommended. The

SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two

external resistors connected to the SS/TRK pin as shown in Figure 35 in the design guide.

Pre-Bias Start up Capability

The LM20136 is in a pre-biased state when the device starts up with an output voltage greater than zero. This

often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these

applications the output can be pre-biased through parasitic conduction paths from one supply rail to another.

Even though the LM20136 is a synchronous converter it will not pull the output low when a pre-bias condition

exists. During start up the LM20136 will not sink current until the Soft-Start voltage exceeds the voltage on the

FB pin. Since the device can not sink current it protects the load from damage that might otherwise occur if

current is conducted through the parasitic paths of the load.

Power Good and Over Voltage Fault Handling

The LM20136 has built in under and over voltage comparators that control the power switches. Whenever there

is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn

on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage

falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output

reaches the UVP threshold the part will continue switching and the PGOOD pin will be asserted and go low.

Typical values for the PGOOD resistor are on the order of 100 k

Ω or less. To avoid false tripping during transient

glitches the PGOOD pin has 16 µs of built in deglitch time to both rising and falling edges.The powergood

behavior for fault conditions is illustrated in Figure 28

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