NOII4SM014KA

Rev. 7 | www.onsemi.com | Page 13 of 25

SPI Register

SPI Interface Architecture

The elementary unit cell of the serial to parallel interface consists of two D-flip-flops. The architecture is shown in Figure 10. 16 of

Figure 10. SPI Interface

SPI Register Definition

Sensor parameters can be serially uploaded inside the sensor at

the start of a frame. The parameters are:

six subsampling modes)

array. Each amplifier can be individually powered up/down

to route the green pixels to the same output amplifiers at all

times. A first bit controls the crossbar. When a second bit is set,

the first bit toggles on every CLK_Y edge to automatically route

the green pixels of the bayer filter pattern.

The code is uploaded serially as a 16-bit word (LSB uploaded

first).

Table 9 on page 14 lists the register definition. The default code

for a full resolution readout is 33342 (decimal) or 1000 0010 0011

1110.

D

Q

C

D

Q

C

Din

To sensor core

Dout

SCLK

CS

16 outputs to sensor core

SCLK

Din

Dout

Unity Cell

Entire uploadable parameter block

CS

D0

D1

D2

D15

CS

SCLK

Din

Ts

Data

valid

Tsclk

Th

Table 8. Timing Requirements Serial Parallel Interface

Parameter

Value

Tsclk

100 ns

Ts

50 ns

Th

50 ns